A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops
نویسندگان
چکیده
A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coarse frequency-locked loop and a fine phase-locked loop with smooth switching to prevent adverse interaction and false locking. Fabricated in a 0.18-μm CMOS process, the recovered clock exhibits a peak-topeak jitter of 60ps for a 2-Gb/s PRBS-7 data and a phase noise of –93.5 dBc/Hz at 1-MHz offset. The core circuit consumes 40 mW at 1.8-V supply and occupies an area of 0.3 mm.
منابع مشابه
1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18- μħbox m CMOS Technology
—A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated-oscillator reset-phase control scheme causes the starting phase of gated-oscillators to alternate repeatedly between 0° and 1...
متن کاملحلقۀ قفل تأخیر پهن باند با پمپ بار خودتنظیم و بدون مشکل عدم تطبیق
Almost all logic systems have a main clock signal in order to provide a common timing reference for all of the components in the system. Supporting the highest bandwidth data rates among devices requires advanced clock management technology such as delay-locked loops (DLLs). The DLL circuitry allows for very precise synchronization of external and internal clocks. In this paper a low jitter and...
متن کاملBurst-Mode Clock Recovery Circuit with a Novel Dual Bit-Rate Structure in 0.n1 8-m CMOS
A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gatedII. GATED-OSCILLATOR BASED CLOCK RECOVERY oscillators to align clock with data edges and can operate in GOCRC (Gated-Oscillator based Clock Recovery half-rate clocking mode, doubling data throughput, as well as Circuit) was originally developed for magnetic drum data in full-rate clocking...
متن کاملA 40-Gb/s Clock and Data Recovery Circuit in 0.18- m CMOS Technology
A phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a quarter-rate bang-bang phase detector. The oscillator is based on differential excitation of a closed-loop transmission line at evenly spaced points, providing half-quadrature phases. The phase detector employs eight flip-flops to sample the input every 12.5 ps, detecting data transitions while retiming...
متن کاملA high speed 0.7μm CMOS PLL circuit for clock/data recovery in interconnection systems
In this paper a CMOS PLL circuit realised for clock and data recovery in interconnection systems is presented. The purpose of this clock recovery PLL is to generate a clock with frequency and phase locked to the input NRZ data, in order to sample them in the optimum point. The topology of the circuit is characterised by two loops, one for the phase lock, the second for a frequency aided acquisi...
متن کامل